1. Field of the Invention
The present invention relates to read only memory devices, for example, but not exclusively to read only memory devices in integrated circuits.
2. Discussion of the Related Art
Memory devices are commonly employed as internal storage areas in computer or processors or other types of electronic equipment.
One of the types of memory devices commonly employed as internal storage is non-volatile semiconductor data storage memory devices such as those commonly referred to as read only memory (ROM). The read only memory device is typically designed to store data in a read only memory array of memory cells. Each memory cell has typically a single transistor per bit of storage. The memory device is characterized in that the ROM is typically hardware pre-programmed during the integrated circuit fabrication process and capable of maintaining the stored data indefinitely and even in the absence of power (as compared against volatile memory such as random access memory (RAM)). Read only memory can be included in any type of integrated circuit such as for example as a read only memory integrated circuit, or as part of a substantial circuit such as an embedded read only memory component within a processor or digital signal processor, controller, or telecommunications integrated circuit. In general the read only memory is used to hold and make available data or code which will not be altered after manufacture.
Typically read only memory arrays of memory cells are defined by a number of transistors arranged in a grid pattern having a plurality of rows and columns. As shown in FIG. 2, each individual transistor of each memory cell of the read only memory is placed between a column of the series of columns and a voltage bus. The column is supplied with power at a first predetermined voltage level referred to as the pre-charged voltage level and the voltage bus is supplied with power at a second different predetermined voltage level. In order to obtain information from the read only memory, a row of memory cells can be activated and all transistors along that row are activated via their respective gates. Along the activated row all the transistors which have been programmed to a “0” data state move their respective columns towards the source voltage bus potential whereas all transistors that have been programmed to a “1” data state will not change their voltage of their associated columns. This can be achieved in some conventional read only memory devices by making or breaking the to coupling between the transistor drain and the associated bit line, while maintaining the coupling of the transistor source to a low source potential and the gate coupled to the transistor associated word line. Thus, as shown in FIG. 2, a transistor, such as transistor 151, programmed with a value of “0” has the coupling between the transistor drain and the bit line ‘made’ and a transistor, such as transistor 161, programmed with a value of “1” has the coupling between the transistor and the bit line broken (or never made or fabricated). The column voltages or voltage levels are sensed from selective columns or bit lines.
Conventional ROM devices although efficient in terms of device components are problematic in many ways.
Firstly, the use a single bit line per bit may require the use of an unbalanced sense amplifier. The high offset required by an unbalanced sense amplifier in turn produces a read only memory design which suffers from both speed and dynamic power issues. The unbalanced differential sensing read only memory suffers from a speed of penalty because of the large bit line discharge required to meet the high offset of the unbalanced sensor amplifier.
Secondly, a conventional read only memory design can also suffer from a high static power loss due to high leakage from the read only memory core array. Furthermore there is a large variation of leakage dependent on the bit line discharge under the varying leakage condition and the large variation of bit line discharge and a device mismatch effects on each read only memory bit cell.
Thirdly the unbalanced differential sensing requires high offset conditions because of the varying process, voltage and temperature conditions which can be employed in the read only memory.